The present invention generally relates to a central processing unit, and more particularly to a central processing unit which processes a predetermined number of bits which is different from the number of bits stored, during one machine cycle, in a memory coupled to the central processing unit via a bus. Further, the present invention is concerned with a system using the above-mentioned central processing unit.
A central processing unit is used together with memories, such as a read only memory and a random access memory, which are coupled to the central processing unit via a bus. In some systems, the number of bits processed by the central processing unit is different from that processed by the memories during one machine cycle. For example, the central processing unit processes 8 bits of data, and each memory stores data for every 16 bits. In this case, data is read out from or written into each memory for every 8 bits.
Referring to FIG. 1, there is illustrated a procedure for executing an addition operation in a system where a central processing unit (hereinafter simply referred to as a CPU) processes data for every 8 bits and a memory stores data for every 16 bits. During cycle 1, an operation code is fetched. A data bus which mutually connects the CPU and the memory carries data for every 8 bits. Thus, during cycle 2, 8-bit low-order data (hereinafter simply referred to as an L data) of 16-bit data to be subjected to the addition operation is read out from the memory and transferred to the CPU via the bus. During cycle 3, 8-bit high-order data (hereinafter simply referred to as an H data) of the 16-bit data is read out from the memory and transferred to the CPU via the bus. Cycle 3 also has a procedure for adding a binary value of 1 to the L data. During cycle 4, the addition result obtained during cycle 3 is written into the memory, and a carry signal indicative of a carry generated in the addition result is added to the H data. During cycle 5 the H data is written into the memory.
However, the above-mentioned prior art has the following disadvantage. Even if the carry is equal to 0 during cycle 4, that is, even if no carry is generated by the operation on the L data, zero is added to the H data, which is then written into the memory during cycle 5. That is, the same data as data read out from the memory during cycle 3 is written into the memory during cycle 5. As a result, cycle 5 is wasteful and thus it takes a long time to complete the operation and obtain the operation result.
In an increment operation (instruction), a carry is generated once for every 256 cycles. Thus, the remaining 255 cycles are wasteful.